rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADP3417 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 dual bootstrapped mosfet driver functional block diagram in vcc overlap protection circuit bst drvh sw drvl pgnd ADP3417 features all-in-one synchronous buck driver bootstrapped high side drive one pwm signal generates both drives anticross-conduction protection circuitry applications multiphase desktop cpu supplies single-supply synchronous buck converters standard-to-synchronous converter adaptations general description the ADP3417 is a dual mosfet driver optimized for driving two n-channel mosfets which are the two switches in a nonisolated synchronous buck power converter. each of the drivers is capable of driving a 3000 pf load with a 20 ns propa- gation delay and a 30 ns transition time. one of the drivers can be bootstrapped and is designed to handle the high voltage sle w rate associated with floating high side gate drivers. the ADP3417 includes overlapping drive protection (odp) to prevent shoot-through current in the external mosfets. the ADP3417 is specified over the commercial temperature r ange of 0 c to 70 c and is available in an 8-lead soic package. in vcc ADP3417 bst drvh sw drvl pgnd delay 1v 12v c bst q1 q2 d1 to inductor 1v figure 1. general application circuit
rev. a e2e ADP3417especifications 1 parameter symbol conditions min typ max unit supply supply voltage range vcc 4.15 13.2 v quiescent current isys vcc = bst = 12 v, in = 0 v 5 7 ma pwm input input voltage high 2 2.5 v input voltage low 2 0.8 v high side driver output resistance, sourcing current v bst ? v sw = 12 v 1.75 3.0 output resistance, sinking current v bst ? v sw = 12 v 1.0 2.5 transition times 3 tr drvh see figure 2, v bst ? v sw = 12 v, 45 55 ns c load = 3 nf transition times 3 tf drvh see figure 2, v bst ? v sw = 12 v, 20 30 ns c load = 3 nf propagation delay 3, 4 tpdh drvh see figure 2, v bst ? v sw = 12 v, 45 65 ns tpdl drvh v bst ? v sw = 12 v 15 35 ns low side driver output resistance, sourcing current vcc = 12 v 1.75 3.0 output resistance, sinking current vcc = 12 v 1.0 2.5 transition times 3 tr drvl see figure 2, vcc = 12 v, 25 35 ns c load = 3 nf tf drvl see figure 2, vcc = 12 v, 21 30 ns c load = 3 nf propagation delay 3, 4 (see figure 2) tpdh drvl see figure 2, vcc = 12 v 30 60 ns tpdl drvl see figure 2, vcc = 12 v 10 20 ns notes 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. 2 logic inputs meet typical cmos i/o conditions for source/sink current (~1 a). 3 ac specifications are guaranteed by characterization but not production tested. 4 for propagation delays, ? tpdh ? refers to the specified signal going high; ? tpdl ? refers to it going low. specifications subject to change without notice. (vcc = 12 v, bst = 4 v to 26 v, t a = 0
rev. a ADP3417 ? absolute maximum ratings * vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to +15 v bst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to +30 v bst to sw . . . . . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to +15 v sw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 5.0 v to +25 v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to vcc + 0.3 v operating ambient temperature range . . . . . . . 0 c to 70 c operating junction temperature range . . . . . . 0 c to 125 c ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 c/w jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 c/w storage temperature range . . . . . . . . . . . . C 65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . 300 c * this is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. unless otherwise specified, all voltages are referenced to pgnd. pin configuration in vcc bst nc drvh sw drvl pgnd nc = no connect ADP3417 top view (not to scale) 1 2 3 4 8 7 6 5 pin function descriptions pin mnemonic function 1 bst floating bootstrap supply for the upper mosfet. a capacitor connected between bst and sw pins holds this bootstrapped voltage for the high side mosfet as it is switched. the capacitor should be chosen between 100 nf and 1 f. 2i nl ogic-level input signal that has primary control of the drive outputs. 3n c no connection 4 vcc input supply. this pin should be bypassed to pgnd with ~1 f ceramic capacitor. 5 drvl synchronous rectifier drive. output drive for the lower (synchronous rectifier) mosfet. 6 pgnd power ground. should be closely connected to the source of the lower mosfet. 7s w this pin is connected to the buck-switching node, close to the upper mosfet s source. it is the floating return for the upper mosfet drive signal. it is also used to monitor the switched voltage to prevent turn- on of the lower mosfet until the voltage is below ~1 v. thus, according to operating conditions, the high low transition delay is determined at this pin. 8 drvh buck drive. output drive for the upper (buck) mosfet. ordering guide temperature package package model range description option ADP3417jr 0 c to 70 c8 -lead standard soic-8 small outline (soic) caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADP3417 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. a ADP3417 e4e in drvh-sw drvl sw t pdl drvl tf drvl v th v th 1v t pdh drvh tr drvh t pdl drvh tr drvl tf drvh t pdh drvl figure 2. nonoverlap timing diagram (timing is referenced to the 90% and 10% points unless otherwise noted)
rev. a ADP3417 e5e t ypical performance characteristicse 1 3 2 t in drvh drvl tpc 1. drvh fall and drvl rise times junction temperature e
rev. a ADP3417 e6e theory of operation the ADP3417 is a dual mosfet driver optimized for driving tw o n-channel mosfets in a synchronous buck converter topol ogy. a single pwm input signal is all that is required to properly drive the high side and the low side fets. each driver is capable of dr iving a 3 nf load. a more detailed description of the ADP3417 and its features follows. refer to the functional block diagram. low side driver th e low side driver is designed to drive low r ds(on) n- channel m osfets. the maximum output resistance for the driver is 3 for sourcing and 2.5 for sinking gate current. the low output resistance allows the driver to have 25 ns rise times and 20 ns fall times into a 3 nf load. the bias to the low side driver is internally connected to the vcc supply and pgnd. when the driver is enabled, the driver ? s output is 180 degrees out of phase with the pwm input. when the ADP3417 is dis- abled, the low side gate is held low. high side driver the high side driver is designed to drive a floating low r ds(on) n-channel mosfet. the maximum output resistance for the d river is 3 for sourcing and 2.5 for sinking gate cur rent. the low output resistance allows the driver to have 45 ns rise times and 20 ns fall times into a 3 nf load. the bias voltage for the high side driver is developed by an external bootstrap supply circuit, which is connected between the bst and sw pins. th e bootstrap circuit comprises a diode, d1, and bootstrap capacitor, c bst . when the ADP3417 is starting up, the sw pin is at ground, so the bootstrap capacitor w ill charge up to vcc th rough d1. when the pwm input goes high, the high side driver will begin to turn the high side mosfet, q1, on by pulling charge out of c bst . as q1 turns on, the sw pin will rise up to v in , forcing the bst pin to v in + v c(bst) , which is enough gate to source voltage to hold q1 on. to complete the cycle, q1 is switched off by pulling the gate down to the volt- age at the sw pin. when the low side mosfet, q2, turns on, the sw pin is pulled to ground. this allows the bootstrap capacitor to charge up to vcc again. the high side driver ? s output is in phase with the pwm input. overlap protection circuit the overlap protection circuit (opc) prevents both of the main power switches, q1 and q2, from being on at the same time. t his is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on-off transitions. the overlap protection c ircuit accomplishes this by adaptively controlling the delay from q1 ? s turn off to q2 ? s turn on and by internally setting the delay from q2 ? s turn off to q1 ? s turn on. to prevent the overlap of the gate drives during q1 ? s turn off a nd q2 ? s turn on, the overlap circuit monitors the voltage at the sw pin. when the pwm input signal goes low, q1 will begin to turn off (after a propagation delay), but before q2 can turn on, the overlap protection circuit waits for the voltage at the sw pin to fall from v in to 1 v. once the voltage on the sw pin has fallen to 1 v, q2 will begin turn on. by waiting for the voltage on the sw pin to reach 1 v, the overlap protection circuit ensures that q1 is off before q2 turns on, regardless of variations in tem- perature, supply voltage, gate charge, and drive current. to prevent the overlap of the gate drives during q2 ? s turn off and q1 ? s turn on, the overlap circuit provides a internal delay that is set to 50 ns. when the pwm input signal goes high, q2 will begin to turn off (after a propagation delay), but before q1 can turn on, the overlap protection circuit waits for the voltage at drvl to drop to around 10% of vcc. once the voltage at drvl has reached the 10% point, the overlap protec- tion circuit will wait for a 50 ns typical propagation delay. once the delay period has expired, q1 will begin turn on. application information supply capacitor selection for the supply input (vcc) of the ADP3417, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. use a 1 f, low esr capacitor. multilayer ceramic chip (mlcc) capacitors provide the best combination of low esr and small size. keep the ceramic capacitor as close as possible to the ADP3417. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c bst ) and a diode, as shown in figure 1. selection of these compo nents can be done after the high side mosfet has been chosen. the bootstrap capacitor must have a voltage rating that is able to handle the maximum supply voltage. a minimum 25 v rating is recommended. the capacitance is determined us ing the following equation: c q v bst gate bst = (1) where, q gate is the total gate charge of the high side mosfet, and v bst is the voltage droop allowed on the high side mosfet drive. for example, the irf7811 has a total gate charge of about 20 nc. for an allowed droop of 200 mv, the required boot- strap capacitance is 100 nf. a good quality ceramic capacitor should be used. a small-signal diode can be used for the bootstrap diode due to the ample gate drive available for the high side mosfet. the bootstrap diode must have a minimum 15 v rating to withstand the maximum boosted supply voltage. the average forward current can be estimated by: iqf f(avg) gate max (2) where f max is the maximum switching frequency of the control- ler. the peak surge current rating should be checked in-circuit, since this is dependent on the source impedance of the 12 v supply and the esr of c bst . printed circuit board layout considerations use the follo wing general guidelines when designing pr inted circuit boards: 1. trace out the high current paths and use short, wide traces to make these connections. 2. connect the pgnd pin of the ADP3417 as close as possible to the source of the lower mosfet. 3. the vcc bypass capacitor should be located as close as possible to vcc and pgnd pins.
rev. a ADP3417 e7e typical application circuits the circuit in figure 3 shows how three ADP3417 drivers can be combined w ith the adp3163 to form a total power conversion solution for v cc(core) generation for an intel pentium ? 4 cpu. in vcc bst drvh sw drvl pgnd nc 7 6 5 1 2 3 4 8 in vcc bst drvh sw drvl pgnd nc 7 6 5 1 2 3 4 8 in vcc bst drvh sw drvl pgnd nc 7 6 5 1 2 3 4 8 l2 600nh q3 fdb7030l c13 15nf r8 2
rev. a e8e c02713e0e8/02(a) printed in u.s.a. ADP3417 8-lead standard small outline package [soic] narrow body (r-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.19 (0.0075) 1.27 (0.0500) 0.41 (0.0160) 0.50 (0.0196) 0.25 (0.0099)
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